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| TECHNICAL DATA IN74LV240 OCTAL BUFFER/LINE DRIVE; 3-STATE The IN74LV240 is a low-voltage Si-gate CMOS device and is pin and function compatible with IN74HC/HCT240. The IN74LV240 is an octal non-inverting buffer/line driver with 3state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The IN74LV240 is identical to the IN74LV244 but has inverting outputs. * * * * * Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 1.2 to 3.6 V Low Input Current: 1.0 A, 0.1 A at O = 25 N Output Current: 8 mA at VCC = 3.0 V High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC DIP 20 1 20 1 DW SUFFIX SO ORDERING INFORMATION IN74LV240N IN74LV240DW IZ74LV240 Plastic DIP SOIC chip TA = -40 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT 1A0 1A1 1A 2 1A 3 2A 0 2A 1 2 4 18 16 1Y 0 1OE 1Y 1 1Y 2 1Y 3 2Y 0 2Y 1 2Y 0 2Y 1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 V CC 2OE 1Y 0 2A 3 1Y 1 2A 2 1Y 2 2A 1 1Y 3 2A 0 1A0 2Y3 1A1 2Y2 1A2 2Y1 1A3 2Y0 6 8 14 12 DATA INPUTS 11 13 9 7 5 INVERTING OUTPUTS 2A0 15 2A1 17 GND 3 OUTPUT ENABLES 1OE 2OE 1 19 FUNCTION TABLE Input nOE L PIN 20=VCC PIN 10 = GND L H nAn L H X Output nYn H L Z H= high level L = low level X = don't care Z = high impedance INTEGRAL 1 IN74LV240 MAXIMUM RATINGS * Symbol VCC IIK * 1 2 Parameter DC supply voltage DC Input diode current DC Output diode current DC Output source or sink current DC VCC current DC GND current Power dissipation per package: * Plastic DIP SO Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds 4 Value -0.5 to +5.0 20 50 35 70 70 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * IO * ICC IGND PD 3 Tstg TL * C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V. * 2 VO < -0.5 V or VO > VCC + 0.5 V. * 3 -0.5 V < VO < VCC + 0.5 V. * 4 Derating - Plastic DIP: - 12 mW/C from 70 to 125C SO Package: : - 8 mW/C from 70 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, t f DC Supply Voltage Input Voltage Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Parameter Min 1.2 0 0 -40 0 0 0 0 Max 3.6 VCC VCC +125 1000 700 500 400 Unit V V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV240 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol Parameter conditions VCC V 25C min VIH HIGH level input voltage 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 VI = VIH or VIL IO = -50 A 1.2 2.0 3.0 3.6 3.0 1.2 2.0 3.0 3.6 3.0 * 1.2 * * 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 max 0.3 0.6 0.9 1.1 0.09 0.09 0.09 0.09 0.33 0.1 0.5 Guaranteed Limit -40C to 85C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.34 max 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.4 1.0 5 125C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.20 max 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.5 1.0 10 V Unit VIL LOW level input voltage V VOH HIGH level output voltage V VI = VIH or VIL IO = -8 mA VOL LOW level output voltage VI = VIH or VIL IO = 50 A V V VI = VIH or VIL IO = 8 mA II IOZ Input current VI = VCC or 0 V V A A Three state leakage 3-state outputs current VI (01,19) = VIH VO =VCC or 0 V Supply current VI =VCC or 0 V IO = 0 A ICC - 8.0 - 80 - 160 A * VCC = 3.3 0.3 V INTEGRAL 3 IN74LV240 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t r=t f=6.0 ns) Test Symbol Parameter conditions VCC V 25C min tPHL, tPLH Propagation delay , 1An to 1Yn, 2An to 2Yn tPHZ tPLZ VI = 0 V or VCC Figure 1 and 3 1.2 2.0 * 1.2 2.0 * 1.2 2.0 * 1.2 2.0 * 3.0 VI = 0 V or VCC max 100 24 15 140 30 20 140 32 20 60 16 10 7.0 50 Guaranteed Limit -40C to 85C min max 125 30 19 175 35 24 175 40 25 75 20 13 7.0 125C min max 150 36 23 210 41 28 210 48 30 90 24 15 7.0 ns Unit Propagation delay, 1OE to VI = 0 V or VCC 1Yn, 2OE to 2Yn Figure 2 and 4 Propagation delay, 1OE to VI = 0 V or VCC 1Yn, 2OE to 2Yn Figure 2 and 4 VI = 0 V or VCC Figure 1 and 3 ns tPZH tPZL ns tTHL, tTLH Output Transition Time, Any Output CI CPD Input capacitance Power dissipation capacitance (per one channel) ns pF pF * VCC = 3.3 0.3 V tr 1An or 2An 10% 90% 50% tf VCC GND t PHL 1Y n or 2Y n 1OE or 2OE t PZL VCC 50% GND t PLZ 50% tPLH 1Ynor 2Y n t THL 90% 50% 10% VCC t PHZ VOL VOH t PZH t TLH 1Ynor 2Y n 50% GND Figure 1. Switching Waveforms TEST POINT Figure 2. Switching Waveforms TEST POINT 1k CL * DEVICE UNDER TEST OUTPUT * CL DEVICE UNDER TEST OUTPUT Connect to VCC when testing tPLZ and tPZL Connect to GND when testing tPHZ and t PZH * Includes all probe and jig capacitance Figure 3. Test Circuit * Includes all probe and jig capacitance Figure 4. Test Circuit INTEGRAL 4 IN74LV240 CHIP PAD DIAGRAM Chip marking EALV240 13 18 1.65+ 0.03 17 19 20 16 15 14 12 11 10 01 09 02 03 Y (0,0) X Location of marking (mm): left lower corner x=1.539, y=1.433. Chip thickness: 0.46 0.02 mm. PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Symbol 1OE 1A 0 2Y3 1A 1 2Y2 2A 2 2Y1 2A 3 2Y0 GND 2A 0 1Y3 2A 1 1Y2 2A 2 1Y1 2A 3 1Y0 2OE VCC Location (left lower corner), mm X 0.115 0.1075 0.3215 0.76 0.9285 1.2115 1.4615 1.674 1.674 1.685 1.674 1.6795 1.674 1.0525 0.7545 0.586 0.293 0.112 0.112 0.112 Y 0.55 0.246 0.131 0.131 0.131 0.131 0.131 0.131 0.43 0.643 1.0855 1.266 1.4345 1.4345 1.4345 1.4345 1.4345 1.4345 1.1385 0.949 Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 04 05 06 07 08 1.9 + 0.03 Note: Pad location is given as per metallization layer INTEGRAL 5 |
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